The present invention relates to ultra-low power integrated circuits (IC), and more particularly to ultra-low power integrated circuits that can switch rapidly from power saving mode to active mode.
In recent years, the explosive growth of battery-powered portable applications, such as cellular phones and laptop computers, has generated tremendous demand for ultra-low power integrated circuits. Sub-threshold circuits, by definition, are integrated circuits designed to operate at power supply voltages lower than the threshold voltages of Complementary Metal Oxide Semiconductor (CMOS) transistors. At sub-threshold operation, transistor currents are reduced by many orders of magnitudes, promising ultra-low power operations. Although studies of sub-threshold circuits have reported promising results with respect to power saving, the technology has yet to be implemented on practical mass production products. A number of critical problems preventing their practical use have been identified:
Performance Problems: Low voltage operation typically can reduce power by one or more orders of magnitudes; however, it also slows down processing speed by one or more orders of magnitudes. Although architectural techniques such as pipelining and parallelism can help compensate for loss in performance, these techniques introduce significant overheads in power and cost. Slow processing speed is not the only performance problem; the worst problem is inconsistency in speed. Under sub-threshold operation, a gate delay can vary by 300% due to natural doping variations. These performance problems will disable most applications.
Stability Problems: Transistors in sub-threshold circuits operate at weak inversion conditions in which the source-drain current is an exponential function of temperature, voltage, and manufacturing parameters. Therefore, non-ideal effects (e.g., process variation, noise) are magnified exponentially, causing severe stability problems. Practical-scale integrated circuits can not operate with such stability problems.
Yield Problems: Due to the sensitivity of sub-threshold circuits, their effective defect density is significantly higher than that of nominal-voltage circuits. As a result, the yield of sub-threshold circuits is significantly lower than nominal voltage circuits, making it impractical to build large-scale integrated circuits.
Test Coverage Problems: Because sub-threshold circuits are sensitive to temperature, voltage, and noise, they are likely to have pattern-dependent or event-dependent failures. Testing methodologies developed for nominal-voltage circuits typically are not adequate for sub-threshold circuits.
Reliability Problems: Reliability failures are typically caused by marginal manufacturing defects that are not significant enough to prevent the IC from passing a production test but can cause failure under use. Test-coverage problems and circuit sensitivity are always followed by reliability problems. Reliability problems are the worst kind of problems due to potentially severe consequences.
In the following discussions, we will call the above problems in performance, stability, yield, test coverage, and reliability as the “sub-threshold problems” because they happen when integrated circuits are under sub-threshold operations. Robustness, consistence, testability, and reliability are absolutely essential requirements for IC technologies. The above problems of sub-threshold circuits outweigh their power saving advantage. These problems must be solved before practical applications of sub-threshold circuits can be built.
We believe power saving sub-threshold technology is extremely valuable because of its commercial and environmental benefits. However, sub-threshold circuits are not ready for practical-scale integrated circuits because of the aforementioned problems. It is therefore highly desirable to develop ultra-low power IC design technology that can avoid the “sub-threshold problems”.
In U.S. Pat. No. 7,307,899 Khellah et al disclosed a method to reduce power consumption in SRAM by dividing memory devices into “banks” that maybe individually put into “sleep mode” via “sleep transistors”. Khellah et al further divide memory banks into “blocks” or “tiles” and execute switching between sleep mode and active mode progressively. The tiles in Khellah et are still too large relative to small block architecture. This patent never mentioned power supply voltages lower than threshold voltages so that this patent is not related to sub-threshold circuits. The mechanisms that switches large blocks of memory cells typically cause performance degradation, and the power overhead needed to support such switching mechanism also can be higher than the power it can save. In U.S. Pat. No. 7,420,834 and in U.S. Pat. No. 7,113,421 Maeda et al disclosed methods to improve read/write noise margins by using lower operation voltages for SRAM write relative to the operation voltages used for SRAM read operations. In U.S. Pat. No. 7,154,770 Islam et al disclosed a similar method. These patents never mentioned power supply voltages lower than threshold voltages so that they are not related to sub-threshold circuits. The mechanisms are also not related to steady-state power savings. In U.S. Pat. No. 6,744,659 Eby et al disclosed a method to reduce SRAM sub-threshold leakage current using body effects of SRAM memory cell transistors. In U.S. Pat. No. 7,092,309 Liaw et al disclosed a method to reduce SRAM power by selectively changing power supply voltages according to word line select signals. In U.S. Pat. No. 7,372,721 Sachdev et al disclosed a method to reduce SRAM leakage current by controlling the virtual ground notes of SRAM memory cells along one column in a memory array. These patents never mentioned power supply voltages lower than threshold voltages so that this patent is not related to sub-threshold circuits. The power saving mechanism is also different. In U.S. Pat. No. 7,397,721 Lee et al disclosed a method for programmable control of SRAM power supply voltage at standby mode. This patent never mentioned power supply voltages lower than threshold voltages so that this patent is not related to sub-threshold circuits. The method applies voltage to large memory array(s) so that the method is not suitable for high speed switching. The power saving mechanism is different. In US. Patent Application No. 2007, 0242,498 Chandrakasan et al disclosed a sub-threshold SRAM cell that comprises 10 transistors (10T). This 10T cell helps to improve stability problems of conventional art sub-threshold SRAM cells, but it still have all the “sub-threshold problems”. These and other references provide partial solutions to SRAM power saving problems, but all of them did not provide the capabilities to switch rapidly from power saving mode to high performance operations modes.
This patent application is a continuation-in-part application of previous patent application with a Ser. No. 12/165,658 and filed by the applicant of this invention on Jul. 1, 2008. The discussions in previous patent application focused on hybrid sub-threshold SRAM devices. This patent application provides additional discussions on hybrid circuits, and more particularly on ultra-low power logic circuits that can switch rapidly from power saving mode to active mode.